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High Density Interconnect Technology

HDI Manufacturing Capabilities

From standard multilayer boards to advanced HDI structures with laser microvias, stacked vias, and via-in-pad technology. Precision-engineered for 5G, automotive, aerospace, and high-performance computing.

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HDI Stack-up & Material

Advanced material selection and layer stack-up configurations supporting the most demanding high-density interconnect requirements.

FeatureStandardAdvanced
Layer CountUp to 40LUp to 100L
Minimum Core Thickness70 µm (2.8 mil)50 µm (2.0 mil)
Minimum Prepreg Thickness60 – 200 µm (2.4 – 7.9 mil)
Base Copper Outer Layer12 – 210 µm12 – 615 µm
Base Copper Inner Layer12 – 210 µm12 – 420 µm
Cu Plating in PTH Via Hole-wall20 – 30 µm20 – 60 µm
PCB Thickness (4L)0.6 – 3.2 mm0.5 – 8.0 mm
PCB Thickness (>10L)1.0 – 3.2 mm0.8 – 8.0 mm
1

FR4 & Halogen-Free FR4

Tg 130°C, 150°C, 170°C options for standard and thermal applications.

2

High-Speed Low Loss

Optimized for signal integrity in 5G and high-frequency designs.

3

Mix Dielectric Stack-ups

Hydrocarbon ceramic, BT, GIL, and PTFE for hybrid constructions.

4

Impedance Control

Review, design adjustment, stack-up service, and detailed test reports on final PCBs.

Laser Vias & Mechanical Drilled Holes

Comprehensive via structuring from standard PTH to advanced stacked and staggered laser microvias.

Parameter Description Standard Advanced
PTH & Buried Hole Drill diameter 0.20 mm (8 mil) 0.15 mm (6 mil)
Finished PTH & Buried Final hole size 0.12 mm (5 mil) 0.07 mm (3 mil)
PTH & Buried Pad Annular ring Drill + 0.25 mm Drill + 0.15 mm
Microvia Laser Drilled Laser hole diameter 0.10 mm (4 mil) 0.06 mm (2.36 mil)
Entry & Capture Pad Microvia pad size Drill + 0.15 mm Drill + 0.12 mm
Skip Via Drill Skip via hole 0.20 mm (8 mil) 0.15 mm (6 mil)
PTH to PTH Minimum spacing 0.30 mm (12 mil) 0.25 mm (10 mil)
PTH to Microvia Minimum spacing 0.25 mm (10 mil) 0.20 mm (8 mil)
Microvia to Microvia Minimum spacing 0.25 mm (10 mil) 0.15 mm (6 mil)
Microvia Dielectric Dielectric thickness 0.06 – 0.08 mm 0.10 mm (4 mil)

Expert Note: HDI mostly contains laser drilled vias but can also contain through vias and buried vias. Staggered, stacked, and skip-via configurations are available depending on layer count and density requirements. Copper-filled microvias and filled & capped buried vias are supported for high-reliability applications.

BGA Pitch Design Values

Optimized trace, space, and via strategies for fine-pitch BGA layouts from 0.8 mm down to 0.5 mm pitch.

ParameterStandardAdvanced
BGA PadMax 0.40 mm (15.75 mil)≥ 0.25 mm (10 mil)
Soldermask OpeningPad + 0.10 mm (4 mil)Pad + 0.08 mm (3.15 mil)
PTH Pad (OL & IL)0.45 mm (17.72 mil)0.40 mm (15.75 mil)
PTH Drill0.20 mm (7.87 mil)
Trace & Space (OL & IL)0.10 / 0.10 mm (4/4 mil)0.075 / 0.075 mm (3/3 mil)
Trace to BGA Pad0.10 mm (4 mil)0.08 mm (3.15 mil)

🎯 Design Strategy

BGA pitch 0.8 mm does not require laser vias or buried vias. A conventional dog-bone design with PTH vias is sufficient. The number of layers is determined by the overall size of the BGA and net count.

  • Dog-bone fanout pattern
  • Standard through-hole vias
  • Cost-optimized layer count
  • Suitable for most automotive & industrial designs
ParameterStandardAdvanced
BGA PadMax 0.35 mm (13.78 mil)≥ 0.25 mm (10 mil)
Soldermask OpeningPad + 0.10 mm (4 mil)Pad + 0.08 mm (3.15 mil)
Microvia Pad (OL & IL)0.30 mm (11.81 mil)0.25 mm (10 mil)
Microvia Hole0.12 mm (5 mil)0.10 mm (4 mil)
Trace & Space (OL)0.10 / 0.10 mm (4/4 mil)0.075 / 0.075 mm (3/3 mil)
Trace to BGA Pad0.10 mm (4 mil)0.08 mm (3.15 mil)

⚡ Design Strategy

BGA pitch 0.65 mm can be achieved with dog-bone design using laser drilled micro-vias. The number of layers and the need for buried vias are determined by the size of the BGA.

  • Laser drilled micro-vias required
  • Dog-bone or near-pad fanout
  • Buried vias optional for density
  • Ideal for telecom and computing
ParameterStandardAdvanced
Microvia0.075 – 0.13 mm (3–5 mil)0.075 – 0.15 mm (3–6 mil)
BGA Pad & IL Capture PadDrill + 0.15 mm (6 mil)Drill + 0.13 mm (5 mil)
Soldermask OpeningPad + 0.10 mm (4 mil)Pad + 0.07 mm (2.76 mil)
Trace & Space (OL & IL)0.10 / 0.10 mm (4/4 mil)0.065 / 0.065 mm (2.56/2.56 mil)
Trace to BGA Pad0.10 mm (4 mil)0.065 mm (2.56 mil)

🔬 Design Strategy

BGA pitch 0.5 mm requires via-in-pad design with laser drilled micro-vias. Micro-vias in BGA pads must be copper-filled to avoid voids during SMT soldering.

  • Via-in-pad (VIP) mandatory
  • Copper-filled micro-vias required
  • Stacked or staggered laser steps
  • High-end mobile & FPGA applications

Physical Dimensions & Tolerances

Tight tolerance control across routing, milling, V-cut scoring, back drilling, and countersink operations.

📐 Routing / Milling

Contour Tolerance±0.1 mm / Adv. ±0.075
Edge to Copper0.25 mm / Adv. 0.15
Hole to Hole Position±0.1 mm / Adv. ±0.075
Min Tool Diameter0.8 mm / Adv. 0.6
Max Panel Dimension580 × 1250 mm

🔺 V-Cut Scoring

Contour Tolerance±0.1 mm
Center to Pattern0.25 ±0.05 mm
V-Cut Angle20° / 30° / 45° / 60°
Angle Tolerance±2° / Adv. ±5°
PCB Thickness Range0.6 – 3.0 mm

🔩 Back Drilling

Depth Tolerance±0.2 mm / Adv. ±0.1
Min Remaining PTH0.4 ±0.2 mm / Adv. 0.2±0.1
Oversize0.25 mm / Adv. 0.1

⛏ Countersink

Hole Angle90° ±10° / Adv. 30–180°
Depth Tolerance±0.2 mm / Adv. ±0.1
Min Remaining0.4 ±0.2 mm / Adv. 0.2±0.1
Tolerance±0.3 mm / Adv. ±0.1

PTH Via Protection

IPC-4761 compliant via protection strategies from simple tenting to fully filled and capped structures.

Type IPC-4761 Ref Fill Material Characteristics
A. Soldermask Tenting N/A Liquid soldermask Most common protection. Risk of exposed Cu in hole over time.
B. Via Filling
Non-conductive or conductive
Type V Soldermask lacquer, epoxy resin, conductive paste Soldermask ≥70% fill; epoxy/conductive require 100%. Excellent hole-wall protection; prevents solder balls on opposite side.
C. Filled + Capped
Both sides
Type VI a&b Soldermask lacquer, epoxy resin, conductive paste Same fill requirements as Type V with additional soldermask cap for complete sealing.
D. Filled + Copper Capped Type VII Epoxy resin, conductive paste Excellent hole-wall protection. Used for stacked microvias, buried vias, and PTH in SMD pads.

Surface Finish Options

Multiple RoHS-compliant surface finishes tailored to soldering complexity, wire bonding, and press-fit requirements.

Surface Finish Thickness RoHS Fine Pitch / BGA Wire Bonding Press-Fit
OSP 0.2 – 0.6 µm
Immersion Tin (Sn) 0.8 – 1.5 µm Limited
Immersion Silver (Ag) 0.1 – 0.5 µm
ENIG (Ni/Au) Ni 3–6 / Au 0.05–0.125 µm Alu Limited
ENEPIG (Ni/Pd/Au) Ni 3–6 / Pd 0.05–0.3 / Au 0.03–0.125 µm Alu / Au
Galvanic Soft Gold Ni 3–6 / Au 0.05–0.8 µm Alu / Au
Galvanic Hard Gold Ni 2.5–6 / Au 0.8–1.5 µm Limited

Expert Note: ENIG is the most common flat surface suitable for multiple soldering processes of high complexity assemblies. The surface is not so sensitive to time between soldering processes. For applications requiring both wire bonding and press-fit, ENEPIG or Galvanic Soft Gold are recommended.

Need an HDI Design Review?

Our FAE team provides free DFM analysis, stack-up recommendations, and impedance simulation for your high-density designs.